RISC-V Atom (Core)

Atom is an open-source 32-bit soft-core processor written in Verilog. It is an embedded class processor architecture that implements the open-source RISC-V instruction set architecture (RV32I), as described in the RISC-V unprivileged spec. Atom contains a two stage pipeline inspired from arm cortex m0+.

The following diagram showcases the architecture of RISC-V Atom core.


Processor Pipeline Stages

The pipeline is divided into two stages. These are explained below.

Stage-1: Fetch

Fetch unit is responsible for fetching instructions from instruction memory through the IBUS. It uses a 32-bit register called “Program counter” to keep track of the address of the instruction being fetched. After the instruction is successfully fetched, Program counter is incremented by 4.

Stage-2: Decode, Execute & Write-back

In this stage, the instruction is decoded, all the signal are assigned in order to configure data-path to execute the instruction. & registers are fetched. A 32 bit immediate is generated by the ImmGen unit. ALU then execute the instruction which is followed by write-back into the register file. Branch calculation also happens in this stage and if branch is taken, the pipeline is flushed. Comparator module in this stage is used for all the instructions that involve comparison like slt, slti, beq, bltu etc.

Processor Interface

RISCV-Atom module is defined in the file RVATOM/rtl/core/atomRV.v. It has has two independent ports which it uses to access memory.

  1. Instruction port &

  2. Data port

Both the ports use a generic ready-valid handshaking protocol to transfer data.

We also provide wrappers to the core to convert the generic handshaking protocol to standard bus protocols such as Wishbobne. These wrappers are specified in the following files.

  1. Wishbobne-B4 Wrapper with separate instruction and data port: RVATOM/rtl/core/atomRV_wb.v

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