Directory Structure

riscv-atom          : root directory
    |
    ├─ docs             : RISCV-Atom documentation & user manual
    |
    ├─ rtl              : RISCV-Atom Verilog Sources
    |   ├─ common           : Common headers
    |   ├─ config           : SoC target config files (JSON)
    |   ├─ core             : RISCV-Atom core components
    |   ├─ dpi              : SystemVerilog DPI sources
    |   ├─ soc              : SoC RTL files
    |   ├─ tb               : Verilog testbenches
    |   └─ uncore           : RISCV-Atom non-core components (SoC peripherals)
    |
    ├─ scripts         : Commonly used python and bash scripts
    |
    ├─ sim              : Atomsim source code
    |   ├─ build            : AtomSim build files (autogenerated)
    |   ├─ docs             : AtomSim Source Documentation (Doxygen)
    |   └─ include          : Third party Libraries for AtomSim
    |
    ├─ sw               : Software sources
    |   ├─ bootloader       : RISC-V Atom bootloader
    |   ├─ examples         : Example programs
    |   └─ lib              : Libc for RISCV-Atom (libcatom)
    |       ├─ include          : Libcatom headers
    |       ├─ libcatom         : Libcatom sources
    |       └─ link             : Linker scripts
    |
    ├─ synth            : RISC-V Atom Synthesis
    |   ├─ altera           : Synthesis project for Altera FPGAs
    |   ├─ xilinx           : Synthesis project for Xilinx FPGAs
    |   └─ yosys            : Synthesis project for Yosys
    |
    ├─ test             : RISCV Atom tests
    |   ├─ riscv-target     : Official RISC-V compliance test files
    |   └─ scar             : SCAR tests directory
    |
    └─ tools            : Utility tools
        └─ elfdump          : Elfdump utility