riscv-atom : root directory
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├─ docs : RISCV-Atom documentation & user manual
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├─ rtl : RISCV-Atom Verilog Sources
| ├─ common : Common headers
| ├─ config : SoC target config files (JSON)
| ├─ core : RISCV-Atom core components
| ├─ dpi : SystemVerilog DPI sources
| ├─ soc : SoC RTL files
| ├─ tb : Verilog testbenches
| └─ uncore : RISCV-Atom non-core components (SoC peripherals)
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├─ scripts : Commonly used python and bash scripts
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├─ sim : Atomsim source code
| ├─ build : AtomSim build files (autogenerated)
| ├─ docs : AtomSim Source Documentation (Doxygen)
| └─ include : Third party Libraries for AtomSim
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├─ sw : Software sources
| ├─ bootloader : RISC-V Atom bootloader
| ├─ examples : Example programs
| └─ lib : Libc for RISCV-Atom (libcatom)
| ├─ include : Libcatom headers
| ├─ libcatom : Libcatom sources
| └─ link : Linker scripts
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├─ synth : RISC-V Atom Synthesis
| ├─ altera : Synthesis project for Altera FPGAs
| ├─ xilinx : Synthesis project for Xilinx FPGAs
| └─ yosys : Synthesis project for Yosys
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├─ test : RISCV Atom tests
| ├─ riscv-target : Official RISC-V compliance test files
| └─ scar : SCAR tests directory
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└─ tools : Utility tools
└─ elfdump : Elfdump utility