Introduction
RISC-V Atom is an open-source soft-core processor platform targeted for FPGAs. It is complete hardware prototyping and software development environment based around Atom, which is a 32-bit embedded-class processor based on the RISC-V Instruction Set Architecture (ISA).
Key Highlights
Key highlights of the RISC-V Atom projects are are listed below:
Atom implements
RV32IC_ZicsrISA as defined in the RISC-V unprivileged ISA manual.Simple 2-stage pipelined architecture, ideal for smaller FPGAs.
Optional support for RISC-V exceptions and interrupts.
Wishbone ready CPU interface.
Interactive RTL simulator - AtomSim.
In-house verification framework - SCAR.
Multiple SoC configurations.
Tiny libc like standard library - Libcatom.
Wide range of example programs.
Open source under MIT License.
Tip
To get started, Check out the getting started guide.
Components
Following is list of various components of the RISC-V Atom project.
A simple 32-bit RISC-V processor.
RISC-V Atom project provides several configurable SoC targets that can be built around the Atom CPU.
AtomSim is the interactive RTL simulator for RISC-V Atom SoCs.
SCAR (Search, Compile Assert, and Run) is an in-house processor verification framework written in python.